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In this application example, we present a simple MEMS design executed with SolidWorks. We then analyze some of the performance and reliability considerations for the modeled structure acting as an electrostatically deflected mirror array, using COSMOS/Works to estimate deflection vs. voltage and the resulting stresses. We suggest approaches to deal with the physics of very small structures as appropriate to modeling MEMS devices with finite element analysis (FEA). Design consideration : For this example, we construct a MEMS array with mirror elements that are 50 ?m x 50 ?m, where the unit cell is 250 ?m square. The mirror element size was chosen to easily handle 20 ?m diameter optical beams, providing margin for misalignment. We demonstrate the design of a square array comprising 100 elements. This geometry is sketched in Figure 1, where we have omitted detail within each unit cell for clarity. The active region within each die is 2.5 mm x 2.5 mm and each die is a square, 4 mm on a side. Figure 2 demonstrates that a typical 8 inch silicon wafer could produce approximately 1,200 dies. Positive photoresist is removed in the exposed regions upon development. Therefore, exposed regions will be bare silicon, which will be directly coated with nickel. After photoresist removal, the anisotropic etch will etch along the <111> crystal planes, resulting in a sidewall angle of 54.74ยบ with the surface. The arrangement of dies on a wafer. For an eight-inch wafer, the side of the square is approximately 140 mm, producing an array of 35 x 35 dies (only 12 x 12 shown). The unit cell geometry for the MEMS mirror design. Dimensions are in millimeters. Deflection Analysis By setting up a design table for the Base component, we have established a technique for evaluating mirror deflection as a function of applied voltage and etch depth of the silicon well. <100> silicon wafers, etched as described above, will exhibit flat terminal planes, parallel to the wafer surface.
Tags : inch silicon wafer, finite element analysis, mirror element, deflection analysis, silicon wafers, inch wafer, optical beams, cell geometry, crystal planes, reliability considerations, square array, sidewall angle, mirror design, positive photoresist, element size
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