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Overviews, The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram, PIN Descriptions, The ATmega128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the ATmega128 is in the ATmega103 compatibility mode. Memory Programming
Program and Data Memory Lock Bits, Register Summary Electrical Characteristics, Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. DS Characteristic, The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega128 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega128 devices, as well as any other device with a proper tLOW acceptance margin.

Tags : atmega128, speed block, risc architecture, memory programming, clock cycle, peripheral units, compatibility mode, pin descriptions, power cmos, programming program, serial interface, max values, power consumption, time requirement, speed 400

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